Staff Application Engineer – ECO Timing

About the Role

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years deep in the trenches of timing signoff and design closure, and you know the difference between a chip that tapes out on schedule and one that misses by three months because someone ignored a critical timing path in the second pass. You are the engineer who gets called when a customer's design is stuck at 95% timing closure and no one can figure out why. You do not just run tools, you understand what the tools are actually doing under the hood, and you know when to trust the results and when to dig deeper. Working across P&R, STA, and ECO flows is second nature to you. You have debugged parasitic extraction issues at 3nm, optimized PPA targets on real silicon projects, and written enough TCL and Perl scripts to automate workflows that used to take days. You are comfortable sitting with a customer's design team in Hyderabad one day and presenting technical tradeoffs to their management the next, translating between 'this violates setup by 200ps' and 'this impacts your product schedule by two weeks.' You do not wait

Requirements & Qualifications

• Proficiency in semiconductor engineering, VLSI design, EDA tooling, or software development.

Perks & Benefits

• Direct application to Synopsys India technical talent team with anti-ghosting tracking.