SOC Engineering, Principal Engineer (STA)

About the Role

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence—from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and execution-focused Static Timing Analysis (STA) engineer with strong fundamentals in timing closure and signoff methodologies. You bring 8+ years of hands-on experience in STA and timing/power closure for advanced nodes (e.g., 16/12/10/7nm; exposure to 5nm is a plus). You are comfortable owning key timing deliverables for blocks and contributing to full-chip closure in collaboration with physical design, synthesis, and verification teams. You have solid experience across the timing closure lifecycle—constraints development and validation, STA signoff, power analysis, and ECO support—and you enjoy solving complex timing issues under aggressive schedules. You communicate clearly, work effectively with global teams, and are motivated to improve productivity through scripting/automation (TCL/Python/Perl). What You’ll Be Doing: Own and execute block-level STA signoff and contribute to full-chip timing closure for advanced process nodes. Perform STA debugging and closure (setup/hold, recovery/removal, clock gating, CDC-related timing assumptions a

Requirements & Qualifications

• Proficiency in semiconductor engineering, VLSI design, EDA tooling, or software development.

Perks & Benefits

• Direct application to Synopsys India technical talent team with anti-ghosting tracking.