Principal RTL Design Engineer, Interconnect IP (PCIe digital design and architecture)

About the Role

Job Title: Principal Digital Design Engineer, PCIe We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years deep in the details of PCIe digital design, and somewhere along the way you became the person others come to when a design decision matters or when something complex needs untangling. You know PCIe architecture not just from specs but from living through silicon bring-up, debugging corner cases at 2 a.m., and watching designs either hold up or fall apart under real-world conditions. That experience shaped how you think about micro-architecture, trade-offs, and what actually ships. You are technical first. You still review RTL. You still care about how a clock domain crossing is handled or whether a state machine will scale to the next generation. But you have also learned how to lead without needing to own every line of code. You set direction, you make the hard calls on architecture, and you help engineers work through problems that do not have obvious answers. You do not wait for perfect clarity. You work with what you have, ask the right questions, align across ver

Requirements & Qualifications

• Proficiency in semiconductor engineering, VLSI design, EDA tooling, or software development.

Perks & Benefits

• Direct application to Synopsys India technical talent team with anti-ghosting tracking.