Principal Engineer- Interface IP Verification (Pre-Silicon- PCIe/CXL/DDR/Ethernet)

About the Role

Principal Engineer- Interface IP Verification (Pre-Silicon-  PCIe/CXL/DDR/Ethernet) We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years verifying silicon that ships into data centers, AI accelerators, and high-performance systems where failure is not an option. The protocols you verify, PCIe, CXL, DDR, Ethernet, are not abstract specs to you. They are living, breathing systems with corner cases that only reveal themselves at 3 a.m. during a regression run, and you are the engineer who finds them before tape-out. You think in layers. You can debug a failing assertion in the UVM environment, trace it back to an RTL timing issue, and then connect it to a protocol compliance gap, all without losing the thread of what actually broke. When someone says 'coverage is at 95%,' you ask which 5% is missing and whether it matters. You do not wait for perfect documentation. Specs are incomplete, architectures evolve, and you have learned to work with what you have, ask the right questions, and build verification environments that adapt as the design matures. You have strong op

Requirements & Qualifications

• Proficiency in semiconductor engineering, VLSI design, EDA tooling, or software development.

Perks & Benefits

• Direct application to Synopsys India technical talent team with anti-ghosting tracking.