Principal ASIC Digital Design Engineer (Verification)

About the Role

We Are   Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.    You Are You have spent over a decade in verification, and you have learned that the difference between a verification flow that works and one that collapses under pressure is usually a decision made at the architecture stage. You are the engineer who catches that decision before it becomes technical debt. You think in systems, not scripts. You know that building verification infrastructure is not about assembling tools, it is about creating an environment where teams can move fast without breaking things.   You have built verification environments from scratch using VCS, Verdi, VMS Execution Manager, and UVM, and you know where each tool shines and where it does not.   What You'll Be Doing   * Architect and implement unified verification flows for Synopsys digital IP products using VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP), and VIPs * Build scalable verification infrastructure from the ground up, designing environments that support complex IP and SoC projects across global teams * Define, document,

Requirements & Qualifications

• Proficiency in semiconductor engineering, VLSI design, EDA tooling, or software development.

Perks & Benefits

• Direct application to Synopsys India technical talent team with anti-ghosting tracking.