Constraints Verification Applications Engineer

About the Role

Alternate Job Titles Constraints Verification Applications Engineer SDC Flow Application Engineer ASIC Constraints AE Timing Constraints Applications Engineer Design Constraints Methodology Engineer We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years living in the space between design intent and what actually gets constrained, and you know that bad SDC is the silent killer of chip schedules. You have seen projects stall because constraints were incomplete, over-constrained, or just plain wrong, and you have learned that getting the constraint flow right early is what separates a clean tapeout from months of painful debug. You are comfortable sitting with a design team, looking at their RTL, their clock architecture, and their constraint files, and spotting the gaps before they become timing closure nightmares. You do not just write SDC, you understand the methodology behind constraint generation, verification, and management across the entire flow from RTL to signoff. You know when a multi-mode, multi-corner setup is incomplete, and you can explain why it matters witho

Requirements & Qualifications

• Proficiency in semiconductor engineering, VLSI design, EDA tooling, or software development.

Perks & Benefits

• Direct application to Synopsys India technical talent team with anti-ghosting tracking.