ASIC Digital Design, Staff Engineer

About the Role

ASIC Digital Design, Staff We Are:  At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence—from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to help transform the future through continuous technological innovation. You Are:  You are a Staff ASIC Digital Design Engineer who owns a PCIe subsystem end to end. You turn architecture into solid micro-architecture and production RTL, and you are the technical owner for that area across configurations, reviews, and debug. You have substantial experience designing complex high-speed interface IP in RTL. You know PCIe well—or you have done equivalent work on CXL, AMBA, DDR, UCIe, or similar protocols. You work across clocking, resets, flow control and low power, and making parameterized RTL maintainable. You can mentor senior and junior designers through reviews and guidance, and you drive issues to closure with verification, formal, and physical design.  What You'll Be Doing: Own RTL and micro-architecture for one or more PCIe controller subsystems or major features (block through subsystem integration). Write design specs, implement production RTL, and drive your area through verification, synthesis/timing closure support, and design convergence. Resolve complex design and debug issues in your d

Requirements & Qualifications

• Proficiency in semiconductor engineering, VLSI design, EDA tooling, or software development.

Perks & Benefits

• Direct application to Synopsys India technical talent team with anti-ghosting tracking.