ASIC Digital Design , Staff Engineer

About the Role

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years building RTL that ships in silicon, not just passes simulation. When you read a protocol specification, you see the corner cases that will break three months into verification, and you architect around them before anyone else notices. You are comfortable taking a huge page Ethernet spec and walking out with a micro-architecture that balances latency, power, and area without needing someone to hold your hand. You write Verilog that other engineers can actually read and maintain. Debugging asynchronous FIFO issues and CDC violations has taught you what good design discipline looks like, and you hold yourself to it even when schedules get tight. Multi-site collaboration does not slow you down. You can review someone's RTL in a different timezone, leave clear feedback, and move the design forward without waiting for a meeting. At Synopsys, you will work on IP cores that power everything from AI accelerators to automotive systems, and the designs you own will matter. What You'll Be Doing Design and code RTL for high-speed

Requirements & Qualifications

• Proficiency in semiconductor engineering, VLSI design, EDA tooling, or software development.

Perks & Benefits

• Direct application to Synopsys India technical talent team with anti-ghosting tracking.