ASIC Digital Design, Principal Engineer

About the Role

We Are:  At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence—from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to help transform the future through continuous technological innovation. You Are:  You are a Principal ASIC Digital Design Engineer and a recognized PCIe technical authority. You set architecture and write and review RTL. You define micro-architecture, make trade-offs across performance, power, area, and configurability, and stay in the design until the IP is silicon-proven. You have shipped complex, highly parameterized high-speed interface IP. You are fluent in PCIe (Gen5/Gen6/Gen7) digital design—transaction layer, data path, link/controller functions, RAS, and power management—and you have working knowledge of adjacent protocols such as CXL, AMBA, DDR, or UCIe. You lead through architecture, design reviews, and direct technical engagement. You mentor senior and staff engineers, resolve complex issues, and represent the design in reviews with verification, physical design, customers, and senior management. What You'll Be Doing: Own PCIe digital architecture and RTL for major controller subsystems, from micro-architecture through design convergence and post-silicon support. Define micro-architecture, design specifications, and

Requirements & Qualifications

• Proficiency in semiconductor engineering, VLSI design, EDA tooling, or software development.

Perks & Benefits

• Direct application to Synopsys India technical talent team with anti-ghosting tracking.